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ISL14011
Data Sheet January 30, 2007 FN6427.0
Low Jitter Clock Generators for Set-Top Box
The ISL14011 series of devices are general purpose integrated Clock Synthesizers and Generators suited for consumer applications such as Set-top Box, and various other consumer applications. The selectable reference input accepts 30MHz signal either from crystal or an external source. It is specified to operate with a nominal 3.3V supply and is offered in 16 Ld QFN package. Contact Factory for other output frequency options.
Features
* LVTTL Outputs * Selectable Crystal or Ref. Clock for Inputs * Period Jitter ~50ps RMS * Single Supply; 3.3V nominal * Extended Temperature Range: -40C to +85C * Available in small foot print package - 16 Ld QFN 3mmx3mm * Pb-Free plus anneal available (RoHS Compliant)
Ordering Information
PART NUMBER ISL14011IRZ* PART MARKING 11IZ TEMP. RANGE (C) -40 to +85 PACKAGE 16 Ld QFN PKG. DWG. # L16.3x3
Applications
* Set-Top Boxes
Pinout
ISL14011 (16 LD QFN) TOP VIEW
CLK4 13 12 NC 11 CLK3 10 CLK2 9 5 GND 6 NC 7 GND 8 CLK1 NC VCC VCC 14 NC 15
*Add "-T" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
VCC 1
16
Selection Table
NUMBER OF OUTPUT PART INPUT OPTIONS FREQUENCY OUTPUTS FREQUENCY PACKAGE ISL14011 30MHz 4 LVTTL 25, 30, 24, 27 16 Ld QFN
X1 2 X2 3 GND 4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL14011 Functional Block Diagram
CLK1 OSC. 30MHz CRYSTAL N1 CLK3 M2 PHASE FREQ DET. VCO2 CLK4 M1 PHASE FREQ DET. VCO1 CLK2
N2
Pin Description
16 LD QFN 1,14,16 2 3 4, 5, 7 8 10 11 13 6, 9,12,15 SYMBOLS VCC X1 X2 GND CLK1 CLK2 CLK3 CLK4 NC Supply Voltage The X1 pin is the terminal 1 of an external 30MHz crystal. This pin is grounded for external CK input. The X2 pin is the terminal 2 of external 30MHz crystal, or external clock input. Ground CLK1 Output: 25MHz CLK2 Output: 30MHz CLK3 Output: 24MHz CLK4 Output: 27MHz No Connect PIN DESCRIPTION
2
FN6427.0 January 30, 2007
ISL14011
Absolute Maximum Ratings
Voltage on VCC, CLK pins (respect to Gnd) . . . . . . . . -0.3V to 4.0V Voltage on X1, X2 pins (respect to Gnd) . . . . . . . . . . . -0.3V to 2.5V ESD Rating MIL STD-883, Method 3014 . . . . . . . . . . . . . . . . . . . . . . . . .>5kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) JC (C/W) 16 Ld QFN Package. . . . . . . . . . . . . . . 59 11.5 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379.
DC Electrical Specifications
SYMBOL Supply Voltage Supply Current
VCC = 3.3V 10%, TA = -40C to +85C, Typical values are at TA = +25C and VCC = 3.3V, Unless otherwise noted SYMBOL VCC ICC CONDITIONS Supply Voltage Supply Current CL = 5pF on all outputs MIN 3.0 TYP 3.3 11 MAX 3.6 15 UNIT V mA
CLOCK INPUT X2 (X1 GROUNDED) FOR EXTERNAL CLOCK MODE Input High Level Input Level Low Input Current CLOCK OUTPUTS (CLK) Output High Level VOH IOH = -100A IOH = -4mA IOH = -6mA Output Low Level VOL IOL = 100A IOL = 4mA IOL = 6mA Output Short Circuit Current IOSC CLK = VCC or Gnd 6 13 VCC-0.2 2.4 2.1 0.2 0.4 0.75 30 V V V V V V mA VIH VIL IIL, IIH VX2 to Ground 0.5 1.5 2.4 0.5 V V mA
AC Electrical Specifications
SYMBOL Crystal Frequency CLOCK OUTPUTS Rise Time Fall Time Duty Cycle Period Jitter Power Up Time
CL= 5pF on all outputs SYMBOL fin CONDITIONS MIN TYP 30 MAX UNIT MHz
tR tF
20% to 80% VCC 80% to 20% VCC 40
1.8 1.8 60 50 2
ns ns % ps ms
JP tPO
RMS VCC >2.7V
3
FN6427.0 January 30, 2007
ISL14011 Typical Performance Curves (Period Jitter)
70 65 PERIOD JITTER SIGMA (ps) 60 55 50 45 40 35 30 25 20 0 2 4 6 8 10 12 14 LOAD CAPACITANCE (pF) CK3 CK4 VSUPPLY = 3.3V TEMPERATURE +23C CK1
CK2
FIGURE 1. STANDARD DEVIATION vs LOAD CAPACITANCE
4
FN6427.0 January 30, 2007
ISL14011 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
2X 0.15 C A A 9 D1 D1/2 6 INDEX AREA N 1 2 3 E1/2 E1 9 2X 0.15 C B 2X 0.15 C A 4X 0 TOP VIEW A2 B E/2 2X 0.15 C B D D/2
L16.3x3
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 A2 A3 b D 0.18 MIN 0.80 NOMINAL 0.90 0.20 REF 0.23 3.00 BSC 2.75 BSC 1.35 1.50 3.00 BSC 2.75 BSC 1.35 1.50 0.50 BSC 0.20 0.30 0.40 16 4 4 0.60 12 0.50 1.65 1.65 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8, 10 9 7, 8, 10 8 2 3 3 9 9 Rev. 1 6/04
E
D1 D2 E E1 E2
A
/ / 0.10 C 0.08 C
e k L
C
SEATING PLANE
SIDE VIEW NX b 5 0.10 D2 7
A3
A1
9
N Nd
4X P (DATUM B) 4X P
MCAB 8
Ne P
D2 2N
NX k
1 (DATUM A) 6 INDEX AREA NX L Ne 8 (Nd-1)Xe REF. BOTTOM VIEW A1 NX b 5 2 3 E2 7 E2/2 8 (Ne-1)Xe REF.
NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
C L
9 CORNER OPTION 4X
SECTION "C-C" C L
9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation.
L1 10 L
L1 e CC
10
L
10. Compliant to JEDEC MO-220VEED-2 Issue C, except for the E2 and D2 MAX dimension.
e TERMINAL TIP FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 5
FN6427.0 January 30, 2007

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